1. Field of the Invention
The present invention generally relates to the field of solid-state memories, particularly to semiconductor memories and, even more particularly, to the field of non-volatile memories. Specifically, the invention relates to non-volatile memories that are electrically programmable.
2. Description of the Related Art
Non-volatile memories are commonly used in several applications when the data stored in the memory device need to be preserved even in absence of power supply. Within the class of non-volatile memories, electrically programmable (and erasable) memories, such as flash memories, have become very popular in applications in which the data to be stored are not immutable (as it might be case of, e.g., a consolidated code for a microprocessor), being instead necessary from time to time to store new data, or to update the data already stored.
Typically, the memory device includes an arrangement of memory cells, disposed for example in rows and columns, so as to form a matrix.
Depending on the way the memory cells in the matrix are interconnected, two classes of flash memories can be identified: those having a so-called NOR architecture, or NOR flash memories, and those having a so-called NAND architecture, shortly referred to as NAND flash memories. Roughly speaking, in a NOR architecture the memory cells of a same matrix column are connected in parallel to a same bit line, whereas in a NAND architecture groups of memory cells of a same matrix column are serially interconnected so as to form respective strings, which strings are then connected in parallel to each other to a same bit line.
Compared to NOR flash memories, NAND flash memories are more compact (a lower number of contacts in the matrix are required), and they are also better suited for applications such as file storage.
In the NAND architecture, the memory space is ideally partitioned into a plurality of memory pages, each page corresponding to a block of memory cells that, in operation, are read or written simultaneously, i.e., in parallel to each other. The number of memory cells in each block determines the size (i.e., the number of bits) of the memory page. Nowadays, memory pages of 8192 cells are rather typical, but larger memory pages are also encountered, for example of 16384 cells.
Clearly, the memory cannot have so high a number of Input/Output (I/O) terminals as to enable transferring in parallel so long data words; usually, eight or sixteen I/O terminals are in fact provided; thus, some kind of “segmentation” of the memory page is necessary for interfacing the memory with the outside world.
To this purpose, a circuit arrangement called “page buffer” is provided in the memory for managing the operations of reading the information stored in the memory cells of a selected memory page, or writing new information thereinto. In very general terms, the page buffer includes a buffer register of size equal to that of the memory page, wherein data read (in parallel) from the memory cells of a selected page are temporarily stored, before being serially outputted in chunks of, e.g., eight or sixteen bits, depending on the number of I/O terminals of the memory; similarly, when data are to be written into the memory, the page buffer is replenished with data received serially in said eight- or sixteen-bits chunks, and, when the buffer has eventually been filled, the data are written in parallel into the memory cells of a given, selected memory page.
The page buffer includes a relatively high number of volatile storage elements, typically bi stable elements or latches, in a number corresponding to the number of memory cells of the memory page.
The basic operations that usually are performed on the memory cells are a “page read” (an operation involving reading data from a selected memory page), a “page program” (writing data into a selected memory page), and an “erase” operation, wherein the storing of the memory cells is erased.
The page buffer typically includes a plurality of read/program units, each one associated with, and operatively couplable to a respective plurality of bit lines, e.g., a pair of bit lines.
From a layout point of view, because of space constraints, it is practically impossible to position the different read/program units directly in correspondence of the corresponding pair of bit lines. In fact, the pitch of a pair of bit lines is much lower than the pitch of the corresponding single read/program unit (which typically includes several transistors).
For this reason, groups of more than one read/program unit, for example four read/program units, may be positioned in a sort of stack along the direction of the bit lines, in the pitch of a corresponding number of, e.g. four pairs of bit lines.
This solution may pose problems in terms of routing of the conductive tracks necessary to bring signals into/out of the read/program units.